FAQ: How does boundary scan work?

Filed under FAQ / JTAG IEEE 1149.1

Q: How does boundary scan work?


IEEE Std 1149.1-1990 and IEEE Std 1149.1a-1993 (a major supplement) define the architecture of the Test Access Port (TAP) and shift-registers implemented in boundary-scan devices.

For boundary scan testing, signal pins of compliant semiconductor devices are typically connected to cells in a parallel-in, parallel-out shift register. This shift-register forms a path around the periphery or the boundary of the semiconductor device. The entry and exit points of the shift register are connected to the TDI and TDO pins respectively, thus allowing access to signal pins. By sending proper "test vectors" down the boundary register, and by enabling test vectors onto the device pins, various tests can be performed.

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